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ltc3555/ltc3555-x 1 3555fd n hdd-based mp3 players, pdas, gps, pmps n portable medical products n handheld instrumentation n other usb-based handheld products features applications description high effciency usb power manager + triple step-down dc/dc the ltc ? 3555 family are highly integrated usb com - patible power management and battery charger ics for li-ion/polymer battery applications. they include a high effciency current limited switching powerpath manager with automatic load prioritization, a battery charger, an ideal diode and three general purpose synchronous step-down switching regulators. the ltc3555 family limits input current to either 100ma or 500ma for usb applications or 1a for adapter-powered applications. unlike linear chargers, the ltc3555 familys switching architecture transmits nearly all of the power available from the usb port to the load with minimal loss and heat which eases thermal constraints in small spaces. two of the three general purpose switching regulators can provide up to 400ma and the third can deliver 1a. the entire product can be controlled via i 2 c or simple i/o. the ltc3555-1/ltc3555-3 versions offer instant-on power delivery to the portable product even with a very low battery voltage. the ltc3555-3 version also has a reduced charger foat voltage of 4.100v for battery safety and longevity. the ltc3555 family is available in the low profle 28-pin (4mm 5mm 0.75mm) qfn surface mount package. high effciency powerpath manager and triple step-down regulator power manager n high effciency switching powerpath? controller with bat-track? adaptive output control n programmable usb or wall current limit (100ma/500ma/1a) n full featured li-ion/polymer battery charger n 1.5a maximum charge current n internal 180m? ideal diode + external ideal diode controller powers load in battery mode n low no-load quiescent current when powered from bat (<32a) dc/dcs n triple high effciency step-down dc/dcs (1a/400ma/400ma i out ) n all regulators operate at 2.25mhz n dynamic voltage scaling on two outputs n i 2 c or independent enable, v out controls n low no-load quiescent current: 20a n 28-pin (4mm 5mm 0.75mm) qfn package switching regulator effciency to system load (p out /p bus ) li-ion 0.8v to 3.6v/400ma 3.3v/25ma 0.8v to 3.6v/400ma 0.8v to 3.6v/1a rst 2 optional 0v t to other loads + ltc3555/ltc3555-x triple high efficiency step-down switching regulators i 2 c port always on ldo memory rtc/low power logic i 2 c core i/o 3555 ta01 processor usb/wall 4.35v to 5.5v charge enable controls usb compliant step-down regulator cc/cv battery charger 5 1 2 3 current control i out (a) 0.01 0 efficiency (%) 20 40 60 80 0.1 1 3555 ta01b 100 10 30 50 70 90 bat = 4.2v bat = 3.3v v bus = 5v i bat = 0ma 10x mode typical application l , lt, ltc and ltm are registered trademarks of linear technology corporation. powerpath and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6522118 and 6404251.
ltc3555/ltc3555-x 2 3555fd absolute maximum ratings v bus (transient) t < 1ms, duty cycle < 1% .......................................... C0.3v to 7v v in1 , v in2 , v in3 , v bus (static), dv cc , fb1, fb2, fb3, ntc, bat, en1, en2, en3, i lim0 , i lim1 , scl, sda, rst3, chrg ............ C0.3v to 6v i clprog .................................................................... 3ma i rst3 , i chrg ............................................................ 50ma i prog ........................................................................ 2ma i ldo3v3 ................................................................... 30m a i sw1 , i sw2 ............................................................ 600ma i sw , i sw3 , i bat , i vout .................................................. 2a junction temperature ........................................... 125c operating temperature range (note 2) .... C40c to 85c storage temperature range ................... C65c to 125c (notes 1, 2, 3) symbol parameter conditions min typ max units powerpath switching regulator v bus input supply voltage 4.35 5.5 v i buslim total input current 1x mode, v out = bat 5x mode, v out = bat 10x mode, v out = bat suspend mode, v out = bat l l l l 87 436 800 0.31 95 460 860 0.38 100 500 1000 0.50 ma ma ma ma i vbusq v bus quiescent current 1x mode, i out = 0ma 5x mode, i out = 0ma 10x mode, i out = 0ma suspend mode, i out = 0ma 7 15 15 0.044 ma ma ma ma 9 10 top view 29 ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 ldo3v3 clprog ntc fb2 v in2 sw2 en2 dv cc gate chrg prog fb1 v in1 sw1 en1 rst3 i lim1 i lim0 sw v bus v out bat scl sda v in3 sw3 en3 fb3 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, v ja = 37c/w exposed pad (pin 29) is gnd, must be soldered to pcb the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3k, unless otherwise noted. pin configuration lead free finish tape and reel part marking* package description temperature range ltc3555eufd#pbf ltc3555eufd#trpbf 3555 28-lead (4mm x 5mm) plastic qfn C40c to 85c ltc3555iufd#pbf ltc3555iufd#trpbf 3555 28-lead (4mm x 5mm) plastic qfn C40c to 85c ltc3555eufd-1#pbf ltc3555eufd-1#trpbf 35551 28-lead (4mm x 5mm) plastic qfn C40c to 85c ltc3555iufd-1#pbf ltc3555iufd-1#trpbf 35551 28-lead (4mm x 5mm) plastic qfn C40c to 85c ltc3555eufd-3#pbf ltc3555eufd-3#trpbf 35553 28-lead (4mm x 5mm) plastic qfn C40c to 85c ltc3555iufd-3#pbf ltc3555iufd-3#trpbf 35553 28-lead (4mm x 5mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ order information electrical characteristics
ltc3555/ltc3555-x 3 3555fd symbol parameter conditions min typ max units h clprog (note 4) ratio of measured v bus current to clprog program current 1x mode 5x mode 10x mode suspend mode 224 1133 2140 11.3 ma/ma ma/ma ma/ma ma/ma i out(powerpath) v out current available before loading bat 1x mode, bat = 3.3v 5x mode, bat = 3.3v 10x mode, bat = 3.3v suspend mode 135 672 1251 0.32 ma ma ma ma v clprog clprog servo voltage in current limit 1x, 5x, 10x modes suspend mode 1.188 100 v mv v uvlo_vbus v bus undervoltage lockout rising threshold falling threshold 3.95 4.30 4.00 4.35 v v v uvlo_vbus-bat v bus to bat differential undervoltage lockout rising threshold falling threshold 200 50 mv mv v out v out voltage 1x, 5x, 10x modes, 0v < bat < 4.2v, i out = 0ma, battery charger off 3.4 bat + 0.3 4.7 v usb suspend mode, i vout = 250a 4.5 4.6 4.7 v f osc switching frequency 1.8 2.25 2.7 mhz r pmos_powerpath pmos on resistance 0.18 r nmos_powerpath nmos on resistance 0.30 i peak_powerpath peak switch current limit 1x, 5x modes 10x 2 3 a a battery charger v float bat regulated output voltage ltc3555/ltc3555-1 ltc3555/ltc3555-1 ltc3555-3 ltc3555-3 l l 4.179 4.165 4.079 4.065 4.200 4.200 4.100 4.100 4.221 4.235 4.121 4.135 v v v v i chg constant current mode charge current r prog = 1k r prog = 5k 980 185 1022 204 1065 223 ma ma i bat battery drain current v bus > v uvlo , battery charger off, i vout = 0a v bus = 0v, i vout = 0a (ideal diode mode) ltc3555 ltc3555-1/ltc3555-3 2 3.5 27 32 5 38 44 a a a v prog prog pin servo voltage 1.000 v v prog_trkl prog pin servo voltage in trickle charge bat < v trkl 0.100 v v c/10 c/10 threshold voltage at prog 100 mv h prog ratio of i bat to prog pin current 1022 ma/ma i trkl trickle charge current bat < v trkl 100 ma v trkl trickle charge threshold voltage bat rising 2.7 2.85 3.0 v v trkl trickle charge hysteresis voltage 135 mv v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination timer starts when bat = v float 3.3 4 5 hour t badbat bad battery termination time bat < v trkl 0.42 0.5 0.63 hour h c/10 end of charge indication current ratio (note 5) 0.088 0.1 0.112 ma/ma electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3k, unless otherwise noted.
ltc3555/ltc3555-x 4 3555fd symbol parameter conditions min typ max units v chrg chrg pin output low voltage i chrg = 5ma 65 100 mv i chrg chrg pin leakage current v chrg = 5v 1 a r on_chg battery charger power fet on resistance (between v out and bat) 0.18 t lim junction temperature in constant temperature mode 110 c ntc v cold cold temperature fault threshold voltage rising threshold hysteresis 75.0 76.5 1.5 78.0 %v bus %v bus v hot hot temperature fault threshold voltage falling threshold hysteresis 33.4 34.9 1.5 36.4 %v bus %v bus v dis ntc disable threshold voltage falling threshold hysteresis 0.7 1.7 50 2.7 %v bus mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na ideal diode v fwd forward voltage v bus = 0v, i vout = 10ma i vout = 10ma 2 15 mv mv r dropout internal diode on resistance, dropout v bus = 0v 0.18 i max_diode internal diode current limit 1.6 a always on 3.3v ldo supply v ldo3v3 regulated output voltage 0ma < i ldo3v3 < 25ma 3.1 3.3 3.5 v r cl_ldo3v3 closed-loop output resistance 4 r ol_ldo3v3 dropout output resistance 23 logic (i lim0 , i lim1 , en1, en2, en3) v il logic low input voltage 0.4 v v ih logic high input voltage 1.2 v i pd1 i lim0 , i lim1 , en1, en2, en3 pull-down currents 2 a i 2 c port dv cc input supply voltage 1.6 5.5 v i dvcc dv cc current scl/sda = 0khz 0.5 a v dvcc_uvlo dv cc uvlo 1.0 v address i 2 c address 0001 001[0] v ih , sda, scl input high threshold 70 %dv cc v il , sda, scl input low threshold 30 %dv cc i pd2 sda, scl pull-down current 2 a v ol digital output low (sda) i pullup = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sta hold time after (repeated) start condition 0.6 s t su_sta repeated start condition setup time 0.6 s electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3k, unless otherwise noted.
ltc3555/ltc3555-x 5 3555fd symbol parameter conditions min typ max units t su_std stop condition time 0.6 s t hd_dat(out) data hold time 225 ns t hd_dat(in) input data hold time 0 900 ns t su_dat data setup time 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t f clock data fall time 20 300 ns t r clock data rise time 20 300 ns t sp spike suppression time 50 ns general purpose switching regulators 1, 2 and 3 v in1,2,3 input supply voltage 2.7 5.5 v v outuvlo v out uvlov out falling v out uvlov out rising v in1,2,3 connected to v out through low impedance. switching regulators are disabled in uvlo 2.5 2.6 2.8 2.9 v v f osc oscillator frequency 1.8 2.25 2.7 mhz i fb1,2,3 fbx input current v fb1,2,3 = 0.85v C50 50 na d 1,2,3 maximum duty cycle 100 % r sw1,2,3_pd swx pull-down in shutdown 10 k general purpose switching regulator 1 i vin1 pulse skip mode input current burst mode input current forced burst mode ? input current ldo mode input current shutdown input current i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a, fb1 = 0v 225 35 20 20 60 35 35 1 a a a a a i limsw1 pmos switch current limit pulse skip/burst mode operation 600 800 1100 ma i out1 available output current pulse skip/burst mode operation (note 7) forced burst mode operation (note 7) ldo mode (note 7) 400 60 50 ma ma ma v fb1 v fb1 servo voltage (note 8) l 0.78 0.80 0.82 v r p1 pmos r ds(on) 0.6 r n1 nmos r ds(on) 0.7 r ldo_cl1 ldo mode closed-loop r out 0.25 r ldo_ol1 ldo mode open-loop r out (note 9) 2.5 general purpose switching regulator 2 i vin2 pulse skip mode input current burst mode input current forced burst mode input current ldo mode input current shutdown input current i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a, fb2 = 0v 225 35 20 20 60 35 35 1 a a a a a i limsw2 pmos switch current limit pulse skip/burst mode operation 600 800 1100 ma i out2 available output current pulse skip/burst mode operation (note 7) forced burst mode operation (note 7) ldo mode (note 7) 400 60 50 ma ma ma electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3k, unless otherwise noted. burst mode is a registered trademark of linear technology corporation.
ltc3555/ltc3555-x 6 3555fd electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v bus = 5v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3k, unless otherwise noted. symbol parameter conditions min typ max units v fbhigh2 maximum servo voltage full scale (1, 1, 1, 1) (note 8) l 0.78 0.80 0.82 v v fblow2 minimum servo voltage zero scale (0, 0, 0, 0) (note 8) 0.405 0.425 0.445 v v lsb2 v fb2 servo voltage step size 25 mv r p2 pmos r ds(on) 0.6 r n2 nmos r ds(on) 0.7 r ldo_cl2 ldo mode closed-loop r out 0.25 r ldo_ol2 ldo mode open-loop r out (note 9) 2.5 general purpose switching regulator 3 i vin3 pulse skip mode input current burst mode input current forced burst mode input current ldo mode input current shutdown input current i out3 = 0a (note 6) i out3 = 0a (note 6) i out3 = 0a (note 6) i out3 = 0a (note 6) i out3 = 0a, fb3 = 0v 225 35 20 20 60 35 35 1 a a a a a i limsw3 pmos switch current limit pulse skip/burst mode operation 1500 2000 2800 ma i out3 available output current pulse skip/burst mode operation (note 7) forced burst mode operation (note 7) ldo mode (note 7) 1000 150 50 ma ma ma v fbhigh3 maximum servo voltage full scale (1, 1, 1, 1) (note 8) l 0.78 0.80 0.82 v v fblow3 minimum servo voltage zero scale (0, 0, 0, 0) (note 8) 0.405 0.425 0.445 v v lsb3 v fb servo voltage step size 25 mv r p3 pmos r ds(on) 0.18 r n3 nmos r ds(on) 0.30 r ldocl3 ldo mode closed loop r out 0.25 r ldool3 ldo mode open loop r out (note 9) 2.5 t rst3 power on reset time for switching regulator v fb3 within 92% of final value to rst3 hi-z 230 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3555e/ltc3555e-x are guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C 40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3555i/ltc3555i-x are guaranteed to meet performance specifcations over the full C40c to 85c operating temperature range. note 3: the ltc3555/ltc3555-x include overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 4: total input current is the sum of quiescent current, i vbusq , and measured current given by: v clprog /r clprog ? (h clprog +1) note 5: h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 6: fbx above regulation such that regulator is in sleep. specifcation does not include resistive divider current refected back to v inx . note 7: guaranteed by design but not explicitly tested. note 8: applies to pulse skip, burst mode operation and forced burst mode operation only. note 9: inductor series resistance adds to open-loop r out .
ltc3555/ltc3555-x 7 3555fd powerpath switching regulator effciency vs output current v bus current vs v bus voltage (suspend) typical performance characteristics ideal diode v-i characteristics ideal diode resistance vs battery voltage output voltage vs output current (battery charger disabled) usb limited battery charge current vs battery voltage usb limited battery charge current vs battery voltage battery drain current vs battery voltage battery charging effciency vs battery voltage with no external load (p b at /p bus ) forward voltage (v) 0 current (a) 0.6 0.8 1.0 0.16 3555 g01 0.4 0.2 0 0.04 0.08 0.12 0.20 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode only v bus = 0v v bus = 5v battery voltage (v) 2.7 resistance () 0.15 0.20 0.25 3.9 3555 g02 0.10 0.05 0 3.0 3.3 3.6 4.2 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode output current (ma) 0 output voltage (v) 4.00 4.25 4.50 800 3555 g03 3.75 3.50 3.25 200 400 600 1000 bat = 4v bat = 3.4v v bus = 5v 5x mode battery voltage (v) 2.7 500 600 700 3.9 3555 g04 400 300 3.0 3.3 3.6 4.2 200 100 0 charge current (ma) v bus = 5v r prog = 1k r clprog = 3k ltc3555 5x usb setting, battery charger set for 1a ltc3555-1/ ltc3555-3 ltc3555-3 battery voltage (v) 2.7 0 charge current (ma) 25 50 75 100 125 150 3.0 3.3 3.6 3.9 3555 g05 4.2 ltc3555 1x usb setting, battery charger set for 1a ltc3555-3 v bus = 5v r prog = 1k r clprog = 3k ltc3555-1/ ltc3555-3 battery voltage (v) 2.7 battery current (a) 15 20 25 3.9 3555 g06 10 5 0 3.0 3.3 3.6 4.2 v bus = 0v v bus = 5v (suspend mode) i vout = 0a output current (a) 0.01 40 efficiency (%) 50 60 70 80 100 0.1 1 3555 g07 90 5x, 10x mode 1x mode bat = 3.8v battery voltage (v) 2.7 efficiency (%) 80 90 100 3.9 3555 g08 70 60 3.0 3.3 3.6 4.2 1x charging efficiency 5x charging efficiency r clprog = 3k r prog = 1k i vout = 0ma ltc3555-3 ltc3555-1/ ltc3555-3 bus voltage (v) 0 quiescent current (a) 30 40 50 4 3555 g09 20 10 0 1 2 3 5 bat = 3.8v i vout = 0ma
ltc3555/ltc3555-x 8 3555fd typical performance characteristics output voltage vs load current in suspend v bus current vs load current in suspend 3.3v ldo output voltage vs load current, v bus = 0v battery charge current vs temperature normalized battery charger float voltage vs temperature low-battery (instant-on) output voltage vs temperature oscillator frequency vs temperature v bus quiescent current vs temperature v bus quiescent current in suspend vs temperature load current (ma) 0 output voltage (v) 4.0 4.5 5.0 0.4 3555 g10 3.5 3.0 2.5 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 3k load current (ma) 0 v bus current (ma) 0.3 0.4 0.5 0.4 3555 g11 0.2 0.1 0 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 3k load current (ma) 0 output voltage (v) 3.0 3.2 20 3555 g12 2.8 2.6 5 10 15 25 3.4 bat = 3v bat = 3.1v bat = 3.2v bat = 3.3v bat = 3.6v bat = 3.5v bat = 3.4v bat = 3.9v, 4.2v temperature (c) ?40 0 charge current (ma) 100 200 300 400 0 40 80 120 3555 g13 500 600 ?20 20 60 100 thermal regulation r prog = 2k 10x mode temperature (c) ?40 normalized float voltage 0.998 0.999 1.000 60 3555 g14 0.997 0.996 ?15 10 35 85 1.001 temperature (c) ?40 output voltage (v) 3.64 3.66 60 3555 g15 3.62 3.60 ?15 10 35 85 3.68 bat = 2.7v i vout = 100ma 5x mode temperature (c) ?40 frequency (mhz) 2.2 2.4 60 3555 g16 2.0 1.8 ?15 10 35 85 2.6 v bus = 5v bat = 3.6v v bus = 0v bat = 3v v bus = 0v bat = 2.7v v bus = 0v temperature (c) ?40 quiescent current (ma) 9 12 60 3555 g17 6 3 ?15 10 35 85 15 v bus = 5v i vout = 0a 5x mode 1x mode temperature (c) ?40 quiescent current (a) 50 60 60 3555 g18 40 30 ?15 10 35 85 70 i vout = 0a
ltc3555/ltc3555-x 9 3555fd typical performance characteristics rst3, chrg pin current vs voltage (pull-down state) 3.3v ldo step response (5ma to 15ma) r ds(on) for switching regulator power switches vs temperature switching regulator current limit vs temperature switching regulator low power mode quiescent currents switching regulator soft-start waveform battery drain current vs temperature switching regulators 1, 2 pulse skip mode quiescent currents switching regulator 3 pulse skip mode quiescent currents rst3, chrg pin voltage (v) 0 rst3, chrg pin current (ma) 60 80 100 4 3555 g19 40 20 0 1 2 3 5 v bus = 5v bat = 3.8v i ldo3v3 5ma/div 0ma 20s/div bat = 3.8v 3555 g20 v ldo3v3 20mv/div ac coupled temperature (c) ?40 battery current (a) 30 40 50 60 3555 g21 20 10 0 ?15 10 35 85 bat = 3.8v v bus = 0v buck regulators off temperature (c) ?40 on-resistance () 0.6 0.8 1.0 60 3555 g22 0.4 0.2 0 ?15 10 35 85 nmos switch nmos switch pmos switch regulators 1, 2 regulator 3 pmos switch temperature (c) ?40 current limit (a) 1.0 1.5 60 3555 g23 0.5 0 ?15 10 35 85 2.0 regulator 3 regulators 1, 2 v in1,2,3 = 3.8v temperature (c) ?40 input current (a) 30 40 50 60 3555 g24 20 10 0 ?15 10 35 85 v in1,2,3 = 3.8v v out1,2,3 = 2.5v burst mode operation ldo mode forced burst mode operation temperature (c) ?40 input current (a) input current (ma) 275 300 325 60 3555 g25 250 225 200 1.85 1.90 1.95 1.80 1.75 1.70 ?15 10 35 85 v out1,2 = 2.5v (constant frequency) v out1,2 = 1.25v (pulse skipping) v in1,2 = 3.8v temperature (c) ?40 input current (a) input current (ma) 300 350 60 3555 g26 250 200 ?15 10 35 85 400 9 10 8 7 11 v in3 = 3.8v (pulse skipping) v in3 = 3.5v (constant frequency) v out3 = 2.5v v out 500mv/div 50s/div 3555 g27
ltc3555/ltc3555-x 10 3555fd typical performance characteristics switching regulators 1, 2 pulse skip mode effciency switching regulators 1, 2 burst mode effciency switching regulators 1, 2 forced burst mode effciency switching regulator 3 pulse skip mode effciency switching regulator 3 burst mode effciency switching regulator 3 forced burst mode effciency switching regulators 1, 2 load regulation at v out1,2 = 1.2v switching regulators 1, 2 load regulation at v out1,2 = 1.8v switching regulators 1, 2 load regulation at v out1,2 = 2.5v load current (ma) 1 40 efficiency (%) 50 60 70 80 10 100 1000 3555 g28 30 20 10 0 90 100 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3555 g29 0 1 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3555 g30 0 1 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v load current (ma) 1 40 efficiency (%) 50 60 70 80 10 100 1000 3555 g31 30 20 10 0 90 100 v out3 = 2.5v v out3 = 1.2v v out3 = 1.8v v in3 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3555 g32 0 1 v out3 = 2.5v v out3 = 1.2v v out3 = 1.8v v in3 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3555 g33 0 1 v out3 = 2.5v v out3 = 1.2v v out3 = 1.8v v in3 = 3.8v load current (ma) 1.185 output voltage (v) 1.200 1.215 1.230 0.1 10 100 1000 3555 g34 1.170 1 v in1,2 = 3.8v burst mode operation forced burst mode operation pulse skip mode load current (ma) 1.778 output voltage (v) 1.800 1.823 1.845 0.1 10 100 1000 3555 g35 1.755 1 v in1,2 = 3.8v burst mode operation forced burst mode operation pulse skip mode load current (ma) 2.47 output voltage (v) 2.50 2.53 2.56 0.1 10 100 1000 3555 g36 2.44 1 v in1,2 = 3.8v burst mode operation forced burst mode operation pulse skip mode
ltc3555/ltc3555-x 11 3555fd pin functions ldo3v3 (pin 1): 3.3v ldo output pin. this pin provides a regulated always-on 3.3v supply voltage. ldo3v3 gets its power from v out . it may be used for light loads such as a watchdog microprocessor or real time clock. a 1f capacitor is required from ldo3v3 to ground. if the ldo3v3 output is not used it should be disabled by connecting it to v out . clprog (pin 2): usb current limit program and moni - tor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin. a fraction of the v bus current is sent to the clprog pin when the synchronous switch of the powerpath switching regulator is on. the switching regulator delivers power until the clprog pin reaches 1.188v. several v bus current limit settings are available via user input which will typically correspond to the 500ma and 100ma usb specifcations. a multi-layer ceramic averaging capacitor or r-c network is required at clprog for fltering. ntc (pin 3): input to the thermistor monitoring circuits. the ntc pin connects to a batterys thermistor to deter - mine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it re-enters the valid range. a low drift bias resistor is required from v bus to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. fb2 (pin 4): feedback input for switching regulator 2. when regulator 2s control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the i 2 c serial port. see table 4. v in2 (pin 5): power input for switching regulator 2. this pin will generally be connected to v out . a 1f mlcc capacitor is recommended on this pin. sw2 (pin 6): power transmission pin for switching regulator 2. en2 (pin 7): logic input. this logic input pin independently enables switching regulator 2. this pin is logically or-ed with its corresponding bit in the i 2 c serial port. see table 2. dv cc (pin 8): logic supply for the i 2 c serial port. if the serial port is not needed it can be disabled by grounding dv cc . when dv cc is grounded, chip control is automati - cally passed to the individual logic input pins. scl (pin 9): clock input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . if dv cc is grounded, the scl pin is equivalent to the b5 bit in the i 2 c serial port. scl in conjunction with sda determine the operating modes of switching regulators 1, 2 and 3 when dv cc is grounded. see tables 2 and 5. sda (pin 10): data input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . if dv cc is grounded, the sda pin is equivalent to the b6 bit in the i 2 c serial port. sda in conjunction with scl determine the operating modes of switching regulators 1, 2 and 3 when dv cc is grounded. see tables 2 and 5. v in3 (pin 11): power input for switching regulator 3. this pin will generally be connected to v out . a 1f mlcc capacitor is recommended on this pin. sw3 (pin 12): power transmission pin for switching regulator 3. en3 (pin 13): logic input. this logic input pin indepen - dently enables switching regulator 3. this pin is logically or-ed with its corresponding bit in the i 2 c serial port. see table 2. fb3 (pin 14): feedback input for switching regulator 3. when regulator 3s control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the i 2 c serial port. see table 4. rst3 (pin 15): logic output. this in an open-drain output which indicates that switching regulator 3 has settled to its fnal value. it can be used as a power-on reset for the primary microprocessor or to enable the other switching regulators for supply sequencing. en1 (pin 16): logic input. this logic input pin indepen - dently enables switching regulator 1. this pin is logically or-ed with its corresponding bit in the i 2 c serial port. see table 2.
ltc3555/ltc3555-x 12 3555fd sw1 (pin 17): power transmission pin for switching regulator 1. v in1 (pin 18): power input for switching regulator 1. this pin will generally be connected to v out . a 1f mlcc capacitor is recommended on this pin. fb1 (pin 19): feedback input for switching regulator 1. when regulator 1s control loop is complete, this pin servos to a fxed voltage of 0.8v. prog (pin 20): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current. if suffcient in- put power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. chrg (pin 21): open-drain charge status output. the chrg pin indicates the status of the battery charger. four possible states are represented by chrg: charging, not charging, unresponsive battery and battery temperature out of range. chrg is modulated at 35khz and switches between a low and a high duty cycle for easy recognition by either humans or microprocessors. see table 1. chrg requires a pull-up resistor and/or led to provide indication. gate (pin 22): analog output. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the ideal diode between v out and bat. the external ideal diode operates in parallel with the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. if the external ideal diode fet is not used, gate should be left foating. bat (pin 23): single cell li-ion battery pin. depending on available v bus power, a li-ion battery on bat will either deliver power to v out through the ideal diode or be charged from v out via the battery charger. v out (pin 24): output voltage of the switching powerpath controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the ltc3555 family will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance ceramic capacitor. v bus (pin 25): primary input power pin. this pin delivers power to v out via the sw pin by drawing controlled cur - rent from a dc source such as a usb port or wall adapter. sw (pin 26): power transmission pin for the usb power path. the sw pin delivers power from v bus to v out via the step-down switching regulator. a 3.3h inductor should be connected from sw to v out . i lim0 , i lim1 (pins 27, 28): logic inputs. i lim0 and i lim1 control the current limit of the powerpath switching regulator. see table 3. both of the i lim0 and i lim1 pins are logically or-ed with their corresponding bits in the i 2 c serial port. see table 2. exposed pad (pin 29): ground. the exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the part. pin functions
ltc3555/ltc3555-x 13 3555fd block diagram 11 14 29 + + ? + ? enable v in3 sw3 fb3 gnd 3555 bd 27 i lim0 21 chrg 2 clprog 3 ntc 28 i lim1 16 en1 7 en2 13 en3 8 dv cc 10 sda 9 scl 1a 2.25mhz switching regulator 3 12 5 4 enable v in2 sw2 fb2 400ma 2.25mhz switching regulator 2 6 18 19 enable v in1 20 prog 23 bat 15mv 0.3v 3.6v ideal 1.188v sw1 fb1 15 rst3 400ma 2.25mhz switching regulator 1 2.25mhz powerpath switching regulator 17 d/a d/a 4 4 i 2 c port i lim decode logic cc/cv charger charge status 22 gate 24 v out sw + ? + ? + ? 3.3v ldo battery temperature monitor suspend ldo 500a 26 ldo3v3 1 25 v bus
ltc3555/ltc3555-x 14 3555fd timing diagram introduction the ltc3555 family are highly integrated power manage - ment ics which include a high effciency switch mode powerpath controller, a battery charger, an ideal diode, an always-on ldo and three general purpose step-down switching regulators. the entire chip is controlled by either direct digital control, by an i 2 c serial port or both. designed specifcally for usb applications, the powerpath controller incorporates a precision average input current step-down switching regulator to make maximum use of the allowable usb power. because power is conserved, the ltc3555 family allows the load current on v out to exceed the current drawn by the usb port without exceeding the usb load specifcations. the powerpath switching regulator and battery charger communicate to ensure that the input current never violates the usb specifcations. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf - fcient or absent power at v bus . an always on ldo provides a regulated 3.3v from available power at v out . drawing very little quiescent current, this ldo will be on at all times and can be used to supply up to 25ma. the three general purpose switching regulators can be independently enabled via either direct digital control or by operating the i 2 c serial port. under i 2 c control, two of the three switching regulators have adjustable set-points so that voltages can be reduced when high processor performance is not needed. along with constant frequency pwm mode, all three switching regulators have a low power burst-only mode setting as well as automatic burst mode operation and ldo modes for signifcantly reduced quiescent current under light load conditions. high effciency switching powerpath controller whenever v bus is available and the powerpath switching regulator is enabled, power is delivered from v bus to v out via sw. v out drives the combination of the external load (switching regulators 1, 2 and 3) and the battery charger. if the combined load does not exceed the powerpath switch - ing regulators programmed input current limit, v out will track 0.3v above the battery. by keeping the voltage across the battery charger low, effciency is optimized because power lost to the linear battery charger is minimized. power available to the external load is therefore optimized. if the combined load at v out is large enough to cause the t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3555 td t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 1 2 3 address wr 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b operation
ltc3555/ltc3555-x 15 3555fd switching power supply to reach the programmed input current limit, the battery charger will reduce its charge cur - rent by that amount necessary to enable the external load to be satisfed. even if the battery charge current is set to exceed the allowable usb current, the usb specifcation will not be violated. the switching regulator will limit the average input current so that the usb specifcation is never violated. furthermore, load current at v out will always be prioritized and only excess available power will be used to charge the battery. if the voltage at bat is below 3.3v, or the battery is not present, and the load requirement does not cause the switching regulator to exceed the usb specifcation, v out will regulate at 3.6v. if the load exceeds the available power, v out will drop to a voltage between 3.6v and the battery voltage. if there is no battery present when the load exceeds the available usb power, v out can drop toward ground. the power delivered from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regulator. to meet the usb maximum load specifcation, the switching regulator includes a control loop which ensures that the average input current is below the level programmed at clprog. the current at clprog is a fraction (h clprog C1 ) of the v bus current. when a programming resistor and an averaging capacitor are connected from clprog to gnd, the voltage on clprog represents the average input current of the switching regulator. when the input current approaches the programmed limit, clprog reaches v clprog , 1.188v, and power out is held constant. the input current limit is programmed by the i lim0 and i lim1 pins or by the i 2 c serial port. it can be confgured to limit average input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the v clprog servo voltage and the resistor on clprog according to the following expression: i vbus = i vbusq + v clprog r clprog ? h clprog + 1 ( ) figure 1 shows the range of possible voltages at v out as a function of battery voltage. the ltc3555 vs the ltc3555-1 and ltc3555-3 for very low battery voltages, the battery charger acts like a load and, due to limited input power, its current will tend to pull v out below the 3.6v instant-on voltage. to prevent v out from falling below this level, the ltc3555-1 and ltc3555-3 include an undervoltage circuit that auto - matic detects that v out is falling and reduces the battery charge current as needed. this reduction ensures that load current and output voltage are always prioritized and yet delivers as much battery charge current as possible. the standard ltc3555 does not include this circuit and thus favors maximum charge current at all times over output voltage preservation. if instant-on operation under low battery conditions is a requirement then the ltc3555-1 or ltc3555-3 should be used. if maximum charge effciency at low battery voltages is preferred, and instant-on operation is not a requirement, then the standard ltc3555 should be selected. all versions of the ltc3555 family will start up with a removed battery. the ltc3555-3 has a battery charger foat voltage of 4.100v rather than the 4.200v foat voltage of the ltc3555 and ltc3555-1. ideal diode from bat to v out the ltc3555 family has an internal ideal diode as well as a controller for an optional external ideal diode. the ideal diode controller is always on and will respond quickly whenever v out drops below bat. if the load current increases beyond the power allowed from the switching regulator, additional power will be operation figure 1. v out vs bat bat (v) 2.4 4.5 4.2 3.9 3.6 3.3 3.0 2.7 2.4 3.3 3.9 3555 f01 2.7 3.0 3.6 4.2 v out (v) no load 300mv
ltc3555/ltc3555-x 16 3555fd pulled from the battery via the ideal diode. furthermore, if power to v bus (usb or wall power) is removed, then all of the application power will be provided by the battery via the ideal diode. the transition from input power to battery power at v out will be quick enough to allow only the 10f capacitor to keep v out from drooping. the ideal diode consists of a precision amplifer that enables a large on-chip p-channel mosfet transistor whenever the voltage at v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approxi - mately 180m. if this is suffcient for the application, then no external components are necessary. however, if more conductance is needed, an external p-channel mosfet transistor can be added from bat to v out . when an external p-channel mosfet transistor is pres - ent, the gate pin of the ltc3555 family drives its gate for automatic ideal diode control. the source of the external p-channel mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the gate pin can control an external p-channel mosfet transistor having an on-resistance of 40m or lower. suspend ldo if the ltc3555 family is confgured for usb suspend mode, the switching regulator is disabled and the suspend ldo provides power to the v out pin (presuming there is power available to v bus ). this ldo will prevent the bat - tery from running down when the portable product has access to a suspended usb port. regulating at 4.6v, this ldo only becomes active when the switching converter is disabled (suspended). to remain compliant with the usb specifcation, the input to the ldo is current limited so that it will not exceed the 500a low power suspend specifcation. if the load on v out exceeds the suspend current limit, the additional current will come from the operation figure 3. powerpath block diagram forward voltage (mv) (bat ? v out ) 0 current (ma) 600 1800 2000 2200 120 240 300 3555 f02 200 1400 1000 400 1600 0 1200 800 60 180 360 480420 vishay si2333 optional external ideal diode ltc3555 ideal diode on semiconductor mbrm120lt3 + ? + + ? 0.3v 1.188v 3.6v clprog i switch / h clprog + ? + ? 15mv ideal diode pwm and gate drive average input current limit controller average output voltage limit controller constant current constant voltage battery charger + ? 2 gate 22 v out 24 sw 3.5v to (bat + 0.3v) to system load optional external ideal diode pmos single cell li-ion 3555 f03 26 bat 23 v bus to usb or wall adapter 25 +
ltc3555/ltc3555-x 17 3555fd battery via the ideal diode. 3.3v always-on ldo supply the ltc3555 family includes a low quiescent current low dropout regulator that is always powered. this ldo can be used to provide power to a system pushbutton controller, standby microcontroller or real time clock. designed to deliver up to 25ma, the always-on ldo requires at least a 1f low impedance ceramic bypass capacitor for com - pensation. the ldo is powered from v out , and therefore will enter dropout at loads less than 25ma as v out falls near 3.3v. if the ldo3v3 output is not used, it should be disabled by connecting it to v out . v bus undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors v bus and keeps the powerpath switching regulator off until v bus rises above 4.30v and is about 200mv above the battery voltage. hysteresis on the uvlo turns off the regulator if v bus drops below 4.00v or to within 50mv of bat. when this happens, system power at v out will be drawn from the battery via the ideal diode. battery charger the ltc3555 family includes a constant-current/ constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out-of-temperature charge pausing. battery preconditioning when a battery charge cycle begins, the battery charger frst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the chrg pin that the battery was unresponsive. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant-current mode. the current delivered to the battery will try to reach 1022v/ r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb current limit programming will always be observed and only additional power will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the voltage on the battery reaches the pre-programmed foat voltage, the battery charger will regulate the battery volt - age and the charge current will decrease naturally. once the battery charger detects that the battery has reached the foat voltage, the four hour safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will auto - matically begin when the battery voltage falls below the recharge threshold which is typically 100mv less than the chargers foat voltage. in the event that the safety timer is running when the battery voltage falls below the recharge threshold, it will reset back to zero. to prevent brief excursions below the recharge threshold from reset - ting the safety timer, the battery voltage must be below the recharge threshold for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus is removed and then replaced), or if the battery charger is cycled on and off by the i 2 c port. charge current the charge current is programmed using a single resis - tor from prog to ground. 1/1022th of the battery charge current is sent to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1022 times the current in the prog pin. the program resistor and the charge current are calculated using the operation
ltc3555/ltc3555-x 18 3555fd following equations: r prog = 1022v i chg , i chg = 1022v r prog in either the constant-current or constant-voltage charging modes, the voltage at the prog pin will be proportional to the actual charge current delivered to the battery. there - fore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i bat = v prog r prog ? 1022 in many cases, the actual battery charge current, i bat , will be lower than i chg due to limited input power available and prioritization with the system load drawn from v out . charge status indication the chrg pin indicates the status of the battery charger. four possible states are represented by chrg which in - clude charging, not charging, unresponsive battery, and battery temperature out of range. the signal at the chrg pin can be easily recognized as one of the above four states by either a human or a mi - croprocessor. an open-drain output, the chrg pin can drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. to make the chrg pin easily recognized by both humans and microprocessors, the pin is either low for charging, high for not charging, or it is switched at high frequency (35khz) to indicate the two possible faults, unresponsive battery and battery temperature out of range. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charging is complete, i.e., the bat pin reaches the foat voltage and the charge current has dropped to one tenth of the programmed value, the chrg pin is released (hi-z). if a fault occurs, the pin is switched at 35khz. while switching, its duty cycle is modulated between a low and high value at a very low frequency. the low and high duty cycles are disparate enough to make an led appear to be on or off thus giving the appearance of blinking. each of the two faults has its own unique blink rate for human recognition as well as two unique duty cycles for machine recognition. the chrg pin does not respond to the c/10 threshold if the ltc3555 family is in v bus current limit. this prevents false end-of-charge indications due to insuffcient power available to the battery charger. table 1 illustrates the four possible states of the chrg pin when the battery charger is active. table 1. chrg signal status frequency modulation (blink) frequency duty cycles charging 0hz 0hz (lo-z) 100% not charging 0hz 0hz (hi-z) 0% ntc fault 35khz 1.5hz at 50% 6.25% to 93.75% bad battery 35khz 6.1hz at 50% 12.5% to 87.5% an ntc fault is represented by a 35khz pulse train whose duty cycle varies between 6.25% and 93.75% at a 1.5hz rate. a human will easily recognize the 1.5hz rate as a slow blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an ntc fault. if a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85v for 1/2 hour), the chrg pin gives the battery fault indication. for this fault, a human would easily recognize the frantic 6.1hz fast blink of the led while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. note that the ltc3555 family is a three terminal powerpath product where system load is always prioritized over battery charging. due to excessive system load, there may not be suffcient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. in this case, the battery charger will falsely indicate a bad battery. system software may then reduce the load and reset the battery charger to try again. although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). when this happens the duty cycle reading will be precisely 50%. if the duty cycle reading is 50%, system software should disqualify it and operation
ltc3555/ltc3555-x 19 3555fd take a new duty cycle reading. ntc thermistor the battery temperature is measured by placing a nega - tive temperature coeffcient (ntc) thermistor close to the battery pack. to use this feature, connect the ntc thermistor, r ntc , between the ntc pin and ground and a resistor, r nom , from v bus to the ntc pin. r nom should be a 1% resistor with a value equal to the value of the chosen ntc therm - istor at 25c (r25). for applications requiring greater than 750ma of charging current, a 10k ntc thermistor is recommended due to increased interference. the ltc3555 family will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 5.4k. for a vishay curve 1 thermistor, this corresponds to approximately 40c. if the battery charger is in constant voltage (foat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the tempera - ture drops, the resistance of the ntc thermistor rises. the ltc3555 family is also designed to pause charging when the value of the ntc thermistor increases to 3.25 times the value of r25. for vishay curve 1 this resistance, 32.5k, corresponds to approximately 0c. the hot and cold comparators each have approximately 3c of hysteresis to prevent oscillation about the trip point. grounding the ntc pin disables the ntc charge pausing function. thermal regulation to optimize charging time, an internal thermal feedback loop may automatically decrease the programmed charge current. this will occur if the die temperature rises to approximately 110c. thermal regulation protects the ltc3555 family from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the part or external components. the beneft of the ltc3555 family thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. i 2 c interface the ltc3555 family may receive commands from a host (master) using the standard i 2 c 2-wire interface. the timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 i 2 c accelerator, are required on these lines. the ltc3555 family is a receive- only slave device. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be connected to the same power supply as the microcontroller generating the i 2 c signals. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below approximately 1v, the i 2 c serial port is cleared and switching regulators 2 and 3 are set to full scale. bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input flters designed to suppress glitches should the bus become corrupted. start and stop conditions a bus-master signals the beginning of a communication to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has fnished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. byte format each byte sent to the ltc3555 family must be eight bits long followed by an extra clock cycle for the acknowledge bit to be returned by the ltc3555 family. the data should be sent to the ltc3555 family most signifcant bit (msb) frst. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) operation
ltc3555/ltc3555-x 20 3555fd operation table 2. i 2 c serial port mapping a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 switching regulator 2 voltage (see table 4) switching regulator 3 voltage (see table 4) disable battery charger switching regulator modes (see table 5) enable regulator 1 enable regulator 2 enable regulator 3 input current limit (see table 3) table 3. usb current limit settings b1 (i lim1 ) b0 (i lim0 ) usb setting 0 0 1x mode (usb 100ma limit) 0 1 10x mode (wall 1a limit) 1 0 suspend 1 1 5x mode (usb 500ma limit) table 5. general purpose switching regulator modes b6 (sda)* b5 (scl)* switching regulator mode 0 0 pulse skip 0 1 forced burst mode operation 1 0 ldo mode 1 1 burst mode operation *sda and scl take on this context only when dv cc = 0v. table 4. switching regulator servo voltage a7 a6 a5 a4 switching regulator 2 servo voltage a3 a2 a1 a0 switching regulator 3 servo voltage 0 0 0 0 0.425v 0 0 0 1 0.450v 0 0 1 0 0.475v 0 0 1 1 0.500v 0 1 0 0 0.525v 0 1 0 1 0.550v 0 1 1 0 0.575v 0 1 1 1 0.600v 1 0 0 0 0.625v 1 0 0 1 0.650v 1 0 1 0 0.675v 1 0 1 1 0.700v 1 1 0 0 0.725v 1 1 0 1 0.750v 1 1 1 0 0.775v 1 1 1 1 0.800v generated by the slave (ltc3555 family) lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the slave-receiver must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. slave address the ltc3555 family responds to only one 7-bit address which has been factory programmed to 0001001. the eighth bit of the address byte (r/w) must be 0 for the ltc3555 family to recognize the address since it is a write only device. this effectively forces the address to be eight bits long where the least signifcant bit of the address is 0. if the correct seven bit address is given but the r/w bit is 1, the ltc3555 family will not respond. bus write operation the master initiates communication with the ltc3555 family with a start condition and a 7-bit address followed by the write bit r/w = 0. if the address matches that of the ltc3555 family, the ltc3555 family returns an acknowl - edge. the master should then deliver the most signifcant data byte. again the ltc3555 family acknowledges and the cycle is repeated for a total of one address byte and two data bytes. each data byte is transferred to an internal holding latch upon the return of an acknowledge. after both data bytes have been transferred to the ltc3555 family, the master may terminate the communication with a stop condition. alternatively, a repeat-start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue indefnitely and the ltc3555 family will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop condition can
ltc3555/ltc3555-x 21 3555fd be sent and the ltc3555 family will update its command latch with the data that it had received. in certain circumstances the data on the i 2 c bus may become corrupted. in these cases the ltc3555 family responds appropriately by preserving only the last set of complete data that it has received. for example, assume the ltc3555 family has been successfully addressed and is receiving data when a stop condition mistakenly occurs. the ltc3555 family will ignore this stop condition and will not respond until a new start condition, correct ad - dress, new set of data and stop condition are transmitted. likewise, with only one exception, if the ltc3555 family was previously addressed and sent valid data but not updated with a stop, it will respond to any stop that appears on the bus, independent of the number of repeat-starts that have occurred. if a repeat-start is given and the ltc3555 family successfully acknowledges its address and frst byte, it will not respond to a stop until both bytes of the new data have been received and acknowledged. disabling the i 2 c port the i 2 c serial port can be disabled by grounding the dv cc pin. in this mode, control automatically passes to the in - dividual logic input pins en1, en2, en3, i lim0 , i lim1 , sda and scl. some functionality is not available in this mode such as the programmability of switching regulators 2 and 3s output voltage and the battery charger disable feature. in this mode, both of the programmable switching regula- tors have a fxed servo voltage of 0.8v. because the sda and scl pins have no other context when dv cc is grounded, these pins are re-mapped to control the switching regulator mode bits b5 and b6. scl maps to b5 and sda maps to b6. rst3 pin the rst3 pin is an open-drain output used to indicate that switching regulator 3 has reached its fnal voltage. rst3 remains low impedance until regulator 3 reaches 92% of its regulation value. a 230ms delay is included to allow a system microcontroller ample time to reset itself. rst3 may be used as a power-on reset to the microprocessor powered by regulator 3 or may be used to enable regulators 1 and/or 2 for supply sequencing. rst3 is an open-drain output and requires a pull-up resistor to the output volt - age of regulator 3 or another appropriate power source. general purpose step-down switching regulators the ltc3555 family contains three general purpose 2.25mhz step-down constant-frequency current mode switching regulators. two regulators provide up to 400ma and a third switching regulator can produce up to 1a. all three switching regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory, disk drive or other logic circuitry. two of the switching regulators have i 2 c programmable set-points for on-the-fy power savings. all three converters support 100% duty cycle operation (low dropout mode) when their input voltage drops very close to their output voltage. to suit a variety of applications, selectable mode functions can be used to trade-off noise for effciency. four modes are available to control the operation of the ltc3555 familys general purpose switching regulators. at moderate to heavy loads, the pulse skip mode provides the least noise switching solution. at lighter loads, either burst mode operation, forced burst mode operation or ldo mode may be selected. the switching regulators include soft-start to limit inrush current when powering on, short-circuit current protection and switch node slew limiting circuitry to reduce radiated emi. no external compensation components are required. the operating mode of the regulators may be set by either i 2 c control or by manual control of the sda and scl pins if the i 2 c port is not used. each converter may be individu - ally enabled by either their external control pins en1, en2, en3 or by the i 2 c port. switching regulators 2 and 3 have individual programmable feedback servo voltages via i 2 c control. the switching regulator input supplies v in1 , v in2 and v in3 will generally be connected to the system load pin v out . step-down switching regulator output voltage programming operation
ltc3555/ltc3555-x 22 3555fd all three switching regulators can be programmed for output voltages greater than 0.8v. switching regulators 2 and 3 have i 2 c programmable set-points while regulator 1 has a single fxed set-point. the full-scale output voltage for each switching regulator is programmed using a resistor divider from the switching regulator output connected to the feedback pins (fb1, fb2 and fb3) such that: v outx = v fbx r1 r2 + 1 ? ? ? ? ? ? where v fbx ranges from 0.425v to 0.8v for switching regulators 2 and 3 and v fbx is fxed at 0.8v for switching regulator 1. see figure 4 typical values for r1 are in the range of 40k to 1m. the capacitor c fb cancels the pole created by feedback resis - to turn on. the n-channel mosfet synchronous rectifer turns off at the end of the 2.25mhz cycle or if the current through the n-channel mosfet synchronous rectifer drops to zero. using this method of operation, the error amplifer adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pwm mode, the inductor current may reach zero on each pulse which will turn off the n-channel mosfet synchronous rectifer. in this case, the switch node (sw) goes high impedance and the switch node voltage will ring. this is discontinuous mode operation, and is normal behavior for a switching regulator. at very light loads in pulse skip mode, the switching regulators will automatically skip pulses as needed to maintain output regulation. at high duty cycles (v outx > v inx /2) it is possible for the inductor current to reverse, causing the regulator to operate continuously at light loads. this is normal and regulation is maintained, but the supply current will increase to several milliamperes due to continuous switching. in forced burst mode operation, the switching regulators use a constant current algorithm to control the inductor current. by controlling the inductor current directly and using a hysteretic control loop, both noise and switching losses are minimized. in this mode output power is limited. while in forced burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the step-down converter then goes into sleep mode, during which the output capacitor provides the load cur - rent. in sleep mode, most of the regulators circuitry is powered down, helping conserve battery power. when the output voltage drops below a pre-determined value, the switching regulator circuitry is powered on and another burst cycle begins. the duration for which the regulator operates in sleep mode depends on the load current. the sleep time decreases as the load current increases. the maximum output current in forced burst mode operation is about 100ma for switching regulators 1 and 2, and about 250ma for switching regulator 3. the step-down switching regulators will not enter sleep mode if the maximum output current is exceeded in forced burst mode operation and the output will drop out of regulation. forced burst mode operation provides a signifcant improvement in effciency operation figure 4. buck converter application circuit tors and the input capacitance of the fb pin and also helps to improve transient response for output voltages much greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most ap - plications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. step-down switching regulator operating modes the ltc3555 familys general purpose switching regulators include four possible operating modes to meet the noise/ power needs of a variety of applications. in pulse skip mode, an internal latch is set at the start of every cycle which turns on the main p-channel mosfet switch. during each cycle, a current comparator compares the peak inductor current to the output of an error amplifer. the output of the current comparator resets the internal latch which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous rectifer v inx ltc3555/ ltc3555-x l swx r1 c out c fb v outx r2 3555 f04 fbx gnd
ltc3555/ltc3555-x 23 3555fd operation ing regulator outputs are individually pulled to ground through a 10k resistor on the switch pins (sw1-sw3) when in shutdown. general purpose switching regulator dropout operation it is possible for a switching regulators input voltage, v inx , to approach its programmed output voltage (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases until it is turned on continuously at 100%. in this dropout condition, the respective output voltage equals the regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. step-down switching regulator soft-start operation soft-start is accomplished by gradually increasing the peak inductor current for each switching regulator over a 500s period. this allows each output to rise slowly, helping minimize the battery surge current. a soft-start cycle occurs whenever a given switching regulator is enabled, or after a fault condition has occurred (thermal shutdown or uvlo). a soft-start cycle is not triggered by changing operating modes. this allows seamless output operation when transitioning between forced burst mode, burst mode, pulse skip mode or ldo operation. step-down switching regulator switching slew rate control the step-down switching regulators contain new patent pending circuitry to limit the slew rate of the switch nodes (swx). this new circuitry is designed to transition the switch nodes over a period of a couple of nanoseconds, signifcantly reducing radiated emi and conducted supply noise. low supply operation the ltc3555 family incorporates an undervoltage lockout circuit on v out which shuts down the general purpose switching regulators when v out drops below v outuvlo . this uvlo prevents unstable operation. at light loads at the expense of higher output ripple when compared to pulse skip mode. for many noise-sensitive systems, forced burst mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e., when the device is in low power standby mode). the i 2 c port can be used to enable or disable forced burst mode operation at any time, offering both low noise and low power operation when they are needed. in burst mode operation, the switching regulator automati - cally switches between fxed frequency pwm operation and hysteretic control as a function of the load current. at light loads, the regulators operate in hysteretic mode in much the same way as described for the forced burst mode operation. burst mode operation provides slightly less output ripple at the expense of slightly lower effciency than forced burst mode operation. at heavy loads the switch - ing regulator operates in the same manner as pulse skip operation at high loads. for applications that can tolerate some output ripple at low output currents, burst mode operation provides better effciency than pulse skip at light loads while still providing the full specifed output current of the switching regulator. finally, the switching regulators have an ldo mode that gives a dc option for regulating their output voltages. in ldo mode, the switching regulators are converted to linear regulators and deliver continuous power from their swx pins through their respective inductors. this mode gives the lowest possible output noise as well as low quiescent current at light loads. the step-down switching regulators allow mode transition on the fy, providing seamless transition between modes even under load. this allows the user to switch back and forth between modes to reduce output ripple or increase low current effciency as needed. step-down switching regulator in shutdown the step-down switching regulators are in shutdown when not enabled for operation. in shutdown, all circuitry in the step-down switching regulator is disconnected from the switching regulator input supply leaving only a few nanoamperes of leakage current. the step-down switch -
ltc3555/ltc3555-x 24 3555fd applications information clprog resistor and capacitor as described in the high effciency switching powerpath controller section, the resistor on the clprog pin deter - mines the average input current limit when the switching regulator is set to either the 1x mode (usb 100ma), the 5x mode (usb 500ma) or the 10x mode. the input cur - rent will be comprised of two components, the current that is used to drive v out and the quiescent current of the switching regulator. to ensure that the usb specifcation is strictly met, both components of input current should be considered. the electrical characteristics table gives values for quiescent currents in either setting as well as current limit programming accuracy. to get as close to the 500ma or 100ma specifcations as possible, a 1% resistor should be used. recall that i vbus = i vbusq + v clprog /r clpprog ? (h clprog +1) an averaging capacitor or an r-c combination is required in parallel with the clprog resistor so that the switching regulator can determine the average input current. this network also provides the dominant pole for the feedback loop when current limit is reached. to ensure stability, the capacitor on clprog should be 0.47f or larger. alternatively, faster transient response may be achieved with 0.1f in series with 8.2 . choosing the powerpath inductor because the average input current circuit does not measure reverse current (i.e., current from sw to v bus ), current reversal in the inductor at light loads will contribute an error to the average v bus current measurement. the error is conservative in that if the current reverses, the voltage at clprog will be higher than what would represent the actual average input current drawn. the current available for battery charging plus system load is thus reduced but the usb specifcation will not be violated. this reduction in available v bus current will happen when the peak-peak inductor ripple is greater than twice the average current limit setting. for example, if the average current limit is set to 100ma, the peak-peak ripple should not exceed 200ma. if the input current is less than 100ma, the measurement accuracy may be reduced. however, this will not affect the average current loop since it will not be in regulation. the ltc3555 family includes a current-reversal com - parator which monitors inductor current and disables the synchronous rectifer as current approaches zero. this comparator will minimize the effect of current reversal on the average input current measurement. for some low inductance values, however, the inductor current may still reverse slightly. this value depends on the speed of the comparator in relation to the slope of the current wave - form, given by v l /l. v l is the voltage across the inductor (approximately Cv out ) and l is the inductance value. an inductance value of 3.3h is a good starting value. the ripple will be small enough for the regulator to remain in continuous conduction at 100ma average v bus current. at lighter loads the current-reversal comparator will dis - able the synchronous rectifer for currents slightly above 0ma. as the inductance is reduced from this value, the ltc3555 family will enter discontinuous conduction mode at progressively higher loads. ripple at v out will increase directly proportionally to the magnitude of inductor ripple. transient response, however, will improve. the current mode controller controls inductor current to exactly the amount required by the load to keep v out in regulation. a transient load step requires the inductor current to change to a new level. since inductor current cannot change instan - taneously, the capacitance on v out delivers or absorbs the difference in current until the inductor current can change to meet the new load demand. a smaller inductor changes its current more quickly for a given voltage drive than a larger inductor, resulting in faster transient response. a larger inductor will reduce output ripple and current ripple, but at the expense of reduced transient performance and a physically larger inductor package size. for this reason a larger c vout will be required for larger inductor sizes. the input regulator has an instantaneous peak current clamp to prevent the inductor from saturating during tran - sient load or start-up conditions. the clamp is designed so that it does not interfere with normal operation at high loads and reasonable inductor ripple. it is intended to pre- vent inductor current runaway in case of a shorted output. the dc winding resistance and ac core losses of the in - ductor will affect effciency, and therefore available output power. these effects are diffcult to characterize and vary
ltc3555/ltc3555-x 25 3555fd by application. some inductors that may be suitable for this application are listed in table 6. table 6. recommended inductors inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018 3.3 2.2 0.08 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc db318c 3.3 3.3 2.26 1.55 0.034 0.070 5 5 3 3.8 3.8 1.8 toko www.toko.com we-tpc type m1 3.3 1.95 0.065 4.8 4.8 1.8 wurth elektronik www.we-online.com cdrh6d12 cdrh6d38 3.3 3.3 2.2 3.5 0.0625 0.020 6.7 6.7 1.5 7 7 4 sumida www.sumida.com v bus and v out bypass capacitors the style and value of capacitors used with the ltc3555 family determine several important parameters such as regulator control-loop stability and input voltage ripple. because the ltc3555 family uses a step-down switching power supply from v bus to v out , its input current wave - form contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load current. increasing the size of this capacitor will reduce the input ripple. to prevent large v out voltage steps during transient load conditions, it is also recommended that a ceramic capaci - tor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 4f of actual capacitance with low esr are required on v out . additional capacitance will improve load transient performance and stability. multilayer ceramic chip capacitors typically have excep - tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have appar - ently higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with caution because of their extreme non-linear characteristic of capacitance verse voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal as is expected in-circuit. many vendors specify the capacitance versus voltage with a 1v rms ac test signal and as a result, overstate the ca - pacitance that the capacitor will present in the application. using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. general purpose switching regulator inductor selection many different sizes and shapes of inductors are avail - able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. the general purpose step-down converters are designed to work with inductors in the range of 2.2h to 10h. for most applications a 4.7h inductor is suggested for the lower power switching regulators 1 and 2 and 2.2h is recommended for the more powerful switching regula - tor 3. larger value inductors reduce ripple current which improves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time. to maximize effciency, choose an inductor with a low dc resistance. for a 1.2v output, effciency is reduced about 2% for 100m series resistance at 400ma load cur - rent, and about 2% for 300m series resistance at 100ma load current. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specifed for the step-down converters. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar applications information
ltc3555/ltc3555-x 26 3555fd electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best effciency. the choice of which style inductor to use often depends more on the price vs size, performance and any radiated emi requirements than on what the ltc3555 family requires to operate. the inductor value also has an effect on forced burst mode and burst mode operations. lower inductor values will cause the burst and forced burst mode switching frequencies to increase. table 7 shows several inductors that work well with the ltc3555 familys general purpose regulators. these in - ductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. table 7. recommended inductors inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer de2818c d312c de2812c 4.7 3.3 4.7 3.3 2.2 4.7 3.3 2.0 1.25 1.45 0.79 0.90 1.14 1.2 1.4 1.8 0.072 0.053 0.24 0.20 0.14 0.13* 0.10* 0.067* 3.0 2.8 1.8 3.0 2.8 1.8 3.6 3.6 1.2 3.6 3.6 1.2 3.6 3.6 1.2 3.0 2.8 1.2 3.0 2.8 1.2 3.0 2.8 1.2 toko www.toko.com cdrh3d16 cdrh2d11 cls4d09 4.7 3.3 2.2 4.7 3.3 2.2 4.7 0.9 1.1 1.2 0.5 0.6 0.78 0.75 0.11 0.085 0.072 0.17 0.123 0.098 0.19 4 4 1.8 4 4 1.8 4 4 1.8 3.2 3.2 1.2 3.2 3.2 1.2 3.2 3.2 1.2 4.9 4.9 1 sumida www.sumida. com sd3118 sd3112 sd12 sd10 4.7 3.3 2.2 4.7 3.3 2.2 4.7 3.3 2.2 4.7 3.3 2.2 1.3 1.59 2.0 0.8 0.97 1.12 1.29 1.42 1.80 1.08 1.31 1.65 0.162 0.113 0.074 0.246 0.165 0.14 0.117* 0.104* 0.075* 0.153* 0.108* 0.091* 3.1 3.1 1.8 3.1 3.1 1.8 3.1 3.1 1.8 3.1 3.1 1.2 3.1 3.1 1.2 3.1 3.1 1.2 5.2 5.2 1.2 5.2 5.2 1.2 5.2 5.2 1.2 5.2 5.2 1.0 5.2 5.2 1.0 5.2 5.2 1.0 cooper www.cooperet. com lps3015 4.7 3.3 2.2 1.1 1.3 1.5 0.2 0.13 0.11 3.0 3.0 1.5 3.0 3.0 1.5 3.0 3.0 1.5 coil craft www.coilcraft. com *typical dcr general purpose switching regulator input/output capacitor selection low esr (equivalent series resistance) mlcc capacitors should be used at both switching regulator outputs as well as at each switching regulator input supply (v inx ). only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 10f output capaci - tor is suffcient for most applications. for good transient response and stability the output capacitor should retain at least 4f of capacitance over operating temperature and bias voltage. each switching regulator input supply should be bypassed with a 1f capacitor. consult with capacitor manufacturers for detailed information on their selection and specifcations of ceramic capacitors. many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 8 shows a list of several ceramic capacitor manufacturers. table 8. recommended ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com over-programming the battery charger the usb high power specifcation allows for up to 2.5w to be drawn from the usb port (5v 500ma). the powerpath switching regulator transforms the voltage at v bus to just above the voltage at bat with high effciency, while limiting power to less than the amount programmed at clprog. in some cases the battery charger may be programmed (with the prog pin) to deliver the maximum safe charging current without regard to the usb specifcations. if there is insuffcient current available to charge the battery at the programmed rate, the powerpath regulator will reduce charge current until the system load on v out is satisfed and the v bus current limit is satisfed. programming the battery charger for more current than is available will not cause the average input current limit to be violated. it will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the battery charger. applications information
ltc3555/ltc3555-x 27 3555fd alternate ntc thermistors and biasing the ltc3555 family provides temperature qualifed charg - ing if a grounded thermistor and a bias resistor are con - nected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are pre-programmed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad- justed by either a modifcation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modifed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tempera - ture trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique are given below. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1002f, used in the following examples, has a nominal value of 10k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of the thermistor at the hot trip point cold = ratio of r ntc|cold to r25 hot = ratio of r ntc|hot to r25 r nom = primary thermistor bias resistor (see figure 5a) r1 = optional temperature range adjustment resistor (see figure 5b) the trip points for the ltc3555 familys temperature quali - fcation are internally programmed at 0.349 ? v bus for the hot threshold and 0.765 ? v bus for the cold threshold. therefore, the hot trip point is set when: r ntc|hot r nom + r ntc|hot s v bus = 0.349 s v bus and the cold trip point is set when: r ntc|cold r nom + r ntc|cold s v bus = 0.765 s v bus solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.536 ? r nom and r ntc|cold = 3.25 ? r nom applications information figure 5. ntc circuits (5a) (5b) ? + ? + r nom 10k r ntc 10k ntc 0.1v ntc_enable 3555 f05a ltc3555/ltc3555-x ntc block too_cold too_hot 0.765 ? v bus 0.349 ? v bus ? + 3 v bus v bus t ? + ? + r nom 10.5k r ntc 10k r1 1.27k ntc v bus v bus 0.1v ntc_enable 3555 f05b too_cold too_hot 0.765 ? v bus 0.349 ? v bus ? + 3 ltc3555/ltc3555-x ntc block t
ltc3555/ltc3555-x 28 3555fd by setting r nom equal to r25, the above equations result in hot = 0.536 and cold = 3.25. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due to the non- linear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r nom = hot 0.536 ? r25 r nom = cold 3.25 ? r25 where hot and cold are the resistance ratios at the desired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, hot is 0.2488 at 60c. using the above equation, r nom should be set to 4.64k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in temperature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be inde- pendently programmed by using an additional bias resistor as shown in figure 5b. the following formulas can be used to compute the values of r nom and r1: r nom = cold ? hot 2.714 ? r25 r1 = 0.536 ? r nom ? hot ? r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose: r nom = 3.266 ? 0.4368 2.714 ? 10k = 10.42k the nearest 1% value is 10.5k: 3ftlotlfl the nearest 1% value is 1.27k. the fnal circuit is shown in figure 5b and results in an upper trip point of 45c and a lower trip point of 0c. usb inrush limiting when a usb cable is plugged into a portable product, the inductance of the cable and the high-q ceramic input capacitor form an l-c resonant circuit. if the cable does not have adequate mutual coupling or if there is not much impedance in the cable, it is possible for the voltage at the input of the product to reach as high as twice the usb voltage (~10v) before it settles out. in fact, due to the high voltage coeffcient of many ceramic capacitors, a nonlinearity, the voltage may even exceed twice the usb voltage. to prevent excessive voltage from damaging the ltc3555 family during a hot insertion, it is best to have a low voltage coeffcient capacitor at the v bus pin to the ltc3555 family. this is achievable by selecting an mlcc capacitor that has a higher voltage rating than that required for the application. for example, a 16v, x5r, 10f capacitor in a 1206 case would be a better choice than a 6.3v, x5r, 10f capacitor in a smaller 0805 case. alternatively, the following soft connect circuit (figure 6) can be employed. in this circuit, capacitor c1 holds mp1 off when the cable is frst connected. eventually c1 begins to charge up to the usb input voltage applying increasing gate support to mp1. the long time constant of r1 and c1 prevent the current from building up in the cable too fast thus dampening out any resonant overshoot. printed circuit board layout considerations in order to be able to deliver maximum current under all conditions, it is critical that the exposed pad on the back - side of the ltc3555 family package be soldered to the pc board ground. failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in higher thermal resistances. furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitors, inductors and output capacitors be as close to the ltc3555 family as possible and that there be an unbroken ground plane under the ic and all of its external high frequency components. applications information
ltc3555/ltc3555-x 29 3555fd high frequency currents, such as the v bus , v in1 , v in2 and v in3 currents on the ltc3555 family, tend to fnd their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to fow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. there should be a group of vias under the grounded backside of the pack - age leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be on the second layer of the pc board. the gate pin for the external ideal diode controller has extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from this pin will introduce an offset to the 15mv ideal diode of approximately 10mv. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less that one volt higher than gate. when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3555 family. 1. are the capacitors at v bus , v in1 , v in2 and v in3 as close as possible to the ltc3555? these capacitors provide the ac current to the internal power mosfets and their drivers. minimizing inductance from these capacitors to the ltc3555 is a top priority. 2. are c out and l1 closely connected? the (C) plate of c out returns current to the gnd plane. 3. keep sensitive components away from the sw pins. battery charger stability considerations the ltc3555 familys battery charger contains both a constant-voltage and a constant-current control loop. the constant-voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, when the battery is dis - connected, a 100f mlcc capacitor in series with a 0.3 resistor from bat to gnd is required to prevent oscillation. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed - back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r prog 1 2 ? 100khz ? c prog applications information figure 6. usb soft connect circuit figure 7. higher frequency ground currents follow their incident path. slices in the ground plane cause high voltage and increased emissions r1 40k 5v usb input 3555 f06 c1 100nf c2 10f mp1 si2333 usb cable v bus gnd ltc3555/ ltc3555-x 3555 f07
ltc3555/ltc3555-x 30 3555fd typical application watchdog microcontroller operation 18 + 26 25 24 23 29 21 22 mp1 c2 22f 10pf li-ion 510 to other loads 1.02m 324k red 3.3v 400ma 1.61v to 3.03v 400ma microprocessor por 0.8v to 1.51v 1a l1 3.3h sw v bus 3 t ntc 20 prog 2 clprog 10k 17 l2 4.7h ltc3555/ ltc3555-x sw1 19 1 fb1 ldo3v3 8 dv cc 9,10 16 7 13 27 28 2 i 2 c v out bat gnd chrg gate 1f 1f 2.2f 10f v in1 5 10pf 1.02m c1: murata grm21br61a106ke19 c2: tdk c2012x5r0j226m l1: coilcraft lps4018-332lm l2, l3: toko 1098as-4r7m l4: toko 1098as-2r0m mp1: siliconix si2333 365k 6 l3 4.7h sw2 4 fb2 i/o core 10f v in2 en1 en2 en3 ilim0 ilim1 11 10pf 715k 806k 12 l4 2h sw3 14 fb3 22f 3555 ta02 v in3 15 rst3 memory 3k 2k 0.1f 8.2 c1 10f usb/wall 4.5v to 5.5v 1f push button microcontroller 10k
ltc3555/ltc3555-x 31 3555fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05
ltc3555/ltc3555-x 32 3555fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2007 lt 0708 rev d ? printed in usa part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter. two high effciency dc/dc converters: up to 96%. full featured li-ion battery charger with accurate usb current limiting (500ma/100ma). pin selectable burst mode operation. hot swap? output for sdio and memory cards. 24-lead 4mm w 4mm qfn package ltc3456 2-cell, multi-output dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources. main output: fixed 3.3v output, core output: adjustable from 0.8v to v batt(min) . hot swap output for memory cards. power supply sequencing: main and hot swap accurate usb current limiting. high frequency operation: 1mhz. high effciency: up to 92%. 24-lead 4mm w 4mm qfn package ltc3552 standalone linear li-ion battery charger with adjustable output dual synchronous buck converter synchronous buck converter, effciency: >90%, adjustable outputs at 800ma and 400ma, charge current programmable up to 950ma, usb compatible, 16-lead 5mm w 3mm dfn package ltc3557/ltc3557-1 usb power manager with li-ion/polymer charger, triple synchronous buck converter plus ldo complete multi function pmic: linear power manager and three buck regulators charge current programmable up to 1.5a from wall adapter input, thermal regulation synchronous buck converters effciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/600ma bat- track? adaptive output control, 200m ideal diode, 4mm 4mm qfn-28 package. ltc4085 usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm w 3mm dfn14 package ltc4088/ltc4088-1/ ltc4088-2 high effciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 4mm w 3mm dfn14 package hot swap and bat-track are trademarks of linear technology corporation. typical application push button start with automatic sequencing, reverse input voltage protection and 10 second push and hold hard shutdown 17 25 8 mp1 usb connector sw1 19 fb1 15 rst3 7 en2 12 sw3 v bus ltc3555/ ltc3555-x dv cc 1 ldo3v3 13 1m mn1 en3 28 ilim1 mn1: 2n7002 mp1: siliconix si2333ds 27 ilim0 0.1f 14 fb3 9,10 i 2 c 1f 1k 4.7k 10k 10f 16 en1 6 2 sw2 4 3555 ta03 fb2 10f memory core i/o scl sda send i 2 c code: ?0x12ff04? once power is detected related parts

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